I notice that the 301 highlights the slight lag between the voltage out on the 101 and the gate out. (The need for 3ms delay on the 301s when doing slice cv control)
So is there anyway that the 101/102 could have a read ahead mode on the programmed cv to effectively create a tighter behaviour and therefore remove the need for the 3ms delay?
What you propose is unfortunately not possible for a sequencer that is slaved to an external clock. The only possible remedy is to build the same delay into the ER-101 gate output but I think quite a few users would not like this.
I would like to add that once unit templates go live on the ER-301, you will be able to set up delays on any gate inputs that need it, save that configuration and have it recreated every time you insert that particular unit.